Modern cryptography has been the guardian of our digital world for half a century. Today, we stand at the threshold of its next evolution.
At Fabric, we empower both cryptographers and cryptography engineers — the innovators and builders — to push boundaries.
Our chip doesn't commit to a single system. Instead, we've accelerated core cryptographic primitives, providing a flexible foundation for transforming breakthrough research into real-world applications.
The Verifiable Processing Unit (VPU) incorporates the best features of GPUs and ASICs to create a chip whose components exclusively serve cryptographic purposes.
Our instruction set is carefully crafted to balance extreme speed for today's workloads, and flexibility for tomorrow's workloads.
Looking for an introduction to Fabric?
Stay tuned! We are giving an overview of our founding thesis, the VPU architecture, and our vision for the future.
End-to-end acceleration with ultra-wide vector lanes, 40 tiles and RISC-V on every chip. High bandwidth, unified memory architecture.
3 FC 1000 chips per card. Nearly 1 TB/s of memory bandwidth to 30 GB of memory. Lovingly known as the "Bit Smasher".
Up to 8 VPU 8060 cards per server. >1 TB/s of recursion-friendly arithmetic hashing per box. A byte's worst nightmare.
Our powerhouse team unites GPU and AI chip architects, software and compiler experts, and veteran cryptographers — all with a decade plus of industry experience.
Our edge: Codesign. Fabric's software, hardware, and cryptography experts collaborate from day one to create breakthrough solutions for programmable trust.
Founder, CSO & Chief Architect of Luminous, a photonic AI chip startup backed by Bill Gates. US Math Olympiad winner. MIT dropout. Bitcoin OG.
Co-inventor of the first MERS-CoV antibody treatment & founder of the first university BioMaker space. Ontology, strategy, vibes. BioE -> Math @ Stanford.
Founder & CTO of DXCorr, 200+ engineers, 100s of custom IP blocks and 70+ full chip tape-outs down to 2nm.
VP SW at Lightelligence, a photonic AI startup. SW/HW co-design expert. AI leader at Meta, Google, Microsoft. EE PhD @ Columbia
VP at Movandi & ASE. Test eng. leader & manufacturing expert across Asia, Europe, and USA. Delivering quality chips on time, every time.
Head of BD / Partnerships at SaaS unicorns Sentry.io, Twilio, Cloudera. 15+ yrs exp driving deep technical partnerships. CS @ Stanford.
Expert in building first in market chips, shipping >10 million parts a week. Hardware security with 25+ years experience.
Leader of high performing, int’l teams down to 5nm designs from AI to cars to medicine. With 35+ years of experience and 25+ tapeouts.
Design Verification leader with 35 years of experience in multiple domains at leading companies including Apple and NVIDIA.
Cryptography HW engineer with 10+ years experience. Previously Entrepreneur First & HW Lead at Zama. PhD in Cryptography @ KULeuven.
CEO & Founder of Radical Semiconductor. Brand, product, and scientific research. BS Physics @ Stanford.
Architect of world-class teams that aim to redefine physical industries. Trusted by Meta, NVIDIA, Luminous and others.
Founding partner of InveStar, first semiconductor VC fund backed by TSMC. Board Director at Monolithic Power Systems & Alchip.
Investor at Blockchain Capital. Former President of Penn Blockchain. Investor in RISC Zero, Eigenlayer, and Blocknative.
Research partner at 1kx. Cryptographer, startup advisor, and formerly research partner at Bain Capital Crypto. PhD in Cryptography from UC San Diego.
